A Study of Dynamic Branch Prediction for SHARC DSPs

Digital signal processors (DSPs) have begun to utilize architectural features typically found on general purpose microprocessors. The impact of using many of these features includes an increased dependence on performance optimizations both in hardware and software. Sophisticated analysis tools are needed in order to better understand the performance implications of these optimizations when applied on DSPs. In this paper we describe how we utilize DSPTune, an execution-driven simulation toolset developed for the SHARC DSP, to analyze the performance advantages of utilizing dynamic branch prediction while running DSP applications. We model two well-known dynamic branch prediction mechanisms using the DSPTune tools, and evaluate the resulting prediction accuracy. While the number of dynamically executed conditional branches is currently small, we are able to evaluate the impact that a branch prediction mechanism might have on future applications targeting DSPs.